1. Field of the Invention
Generally, the present disclosure relates to the fabrication of highly sophisticated integrated circuits including transistor elements having non-planar channel architecture.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a planar transistor architecture, the distance between the source and drain regions, which is also referred to as channel length.
Presently, the vast majority of integrated circuits are formed on the basis of silicon due to its substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the past 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and thus allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide has been preferably used as a base material for gate insulation layers that separate the gate electrode, frequently comprised of polysilicon or other metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by, among other things, the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length for a planar transistor configuration requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced variance of the threshold voltage. Aggressively scaled planar transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current due to the required enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly reduced to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm.
For these reasons, a plurality of alternative approaches have been developed in an attempt to further enhance performance of planar transistors while avoiding the above-described problems. For instance, replacing silicon dioxide as material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide gate layers. For example, dielectric material with significantly increased dielectric constant may be used, such as hafnium oxide and the like. Therefore, sophisticated approaches have been developed in order to provide gate electrode structures formed on the basis of superior gate dielectric materials, so-called high-k dielectric materials. In addition to the superior high-k dielectric materials, also metal-containing electrode materials are used in order to achieve enhanced overall conductivity of the gate electrode structures and provide efficient mechanisms for appropriately adjusting the work function for the various types of transistors. For example, the high-k dielectric material may be provided in an early manufacturing stage, i.e., upon patterning the gate electrode structure, or may be provided in a very advanced manufacturing stage, along with highly conductive electrode metals, by applying a so-called replacement gate approach. Although these approaches for providing sophisticated gate electrode structures contribute to significant enhancement of the performance characteristics of the transistors, there are still significant issues upon further scaling the overall dimensions of the transistors.
According to other strategies, performance of planar transistors may be efficiently increased by modifying the lattice structure in silicon-based semiconductor materials. As is well known, tensile or compressive strain may significantly change the charge carrier mobility in silicon-based semiconductor materials, thereby allowing significantly enhanced performance of planar transistors. For instance, for a standard crystallographic orientation of a silicon-based material, the generation of a tensile strain component along the current flow direction of the channel region of a planar transistor may significantly increase mobility of electrons and, thus, switching speed and drive current capability of the transistor may be increased. On the other hand, for the same standard crystallographic configuration, uniaxial compressive strain in the channel region may enhance mobility of holes, thereby providing the possibility of increasing performance of P-channel transistors. A corresponding strain component may be obtained by providing globally strained semiconductor materials in which corresponding active regions of transistors may be formed. In other well-established process techniques, the strain may be locally generated in the channel region of the transistors by implementing various strain-inducing mechanisms, such as incorporating a strain-inducing semiconductor material in the drain and source regions of N-channel transistors and/or P-channel transistors. For instance, providing a silicon/germanium alloy in the drain and source regions may result, due to the lattice mismatch between the silicon-based material and the silicon/germanium alloy, in a strained configuration, thereby inducing a substantially uniaxial compressive strain component, which may thus increase performance of P-channel transistors. Furthermore, other well-established strain-inducing mechanisms may be applied in the form of highly stressed materials positioned in close proximity to the transistors, thereby also inducing a desired strain component. For this purpose, the interlayer dielectric material provided in the contact level of the transistor elements may be used to induce a desired type of strain.
FIG. 1a schematically illustrates a perspective view of a sophisticated semiconductor device 100 comprising a planar transistor 150, which may be used in complex logic circuits, such as CPUs and the like, in order to obtain a high switching speed and the required drive current, as may be necessary for sophisticated applications. As illustrated, the conventional device 100 may comprise a substrate 101, such as a silicon substrate and the like, possibly in combination with a buried insulating layer 102, thereby providing a silicon-on-insulator (SOI) architecture, which may generally provide certain advantages in terms of switching speed and the like. Moreover, a silicon-based semiconductor layer 103 is formed on the buried insulating layer 102 and may comprise a plurality of “active” regions 103a which are laterally delineated by isolation structures, such as shallow trench isolations and the like. It should be appreciated that an active region is to be understood as a semiconductor region in which appropriate PN junctions are formed or are to be formed for at least one transistor element. In the example shown, the active region 103a comprises a source region 152s and a drain region 153d, which may represent highly doped semiconductor regions so as to provide a moderately high conductivity and to form a PN junction with a channel region 154 positioned between the source region 152s and the drain region 153d. In the case of a P-channel enrichment transistor, drain and source regions 153d, 152s may be P-doped, while the channel region 154 may be slightly N-doped. Thus, for achieving a high drive current of the transistor 150 in the case of a P-channel transistor, the channel region 154 has to be enriched with holes as charge carriers so as to enable a P-conductive path from the source region 152s to the drain region 153d. For an N-channel transistor, inversely doped drain and source regions and a channel region has to be provided. Furthermore, the transistor 150 comprises a gate electrode structure 151, which may comprise an electrode material 151a that is formed on a gate dielectric material 151b, which thus separates the electrode material 151a from the channel region 154. Furthermore, frequently, a spacer structure 151c may be formed on sidewalls of the electrode material 151a, wherein, for convenience, the spacers 151c are illustrated so as to be transparent in order to not unduly obscure the illustration of the transistor 150.
The interface between the channel region 154 and the gate dielectric material 151b may substantially determine the electronic characteristics of the transistor 150, wherein this interface is provided within a single plane so that the transistor 150 may be considered as a planar transistor device. As previously explained, one important parameter of the transistor 150 is represented by the length of the gate electrode structure 151, which may be understood as the horizontal extension of the electrode material 151a. For instance, in sophisticated applications, the gate length is approximately 50 nm and less, which may thus require a high capacitive coupling of the electrode material 151a to the channel region 154 via the gate dielectric material 151b. Consequently, the thickness and/or the material composition of the gate dielectric material 151b have to be appropriately selected in order to provide the desired capacitive coupling. Furthermore, the overall drive current of the transistor 150 is also determined by the transistor width, since the width determines the total area available for the charge carrier transport.
Due to the limitations with respect to leakage currents of gate dielectric material and due to the complexity of patterning gate electrode structures and active regions for achieving the required high drive current capability in combination with a high switching speed, additional mechanisms have been implemented in order to create a desired type of strain 156 in the channel region 154. For example, a strain-inducing semiconductor alloy 155 may be incorporated into the drain and source regions 152s, 153d which may have a strained state and which may thus induce the strain 156. Additionally or alternatively to the strain-inducing material 155, the spacer structure 151c may be provided as a highly stressed dielectric material and/or a further material may be formed on the drain and source regions 152s, 153d in a highly stressed state, thereby also inducing a certain degree of strain in the channel region 154. Although these mechanisms may provide significant enhancement of transistor performance for a given geometric configuration of the transistor 150, upon further device scaling, i.e., upon further reducing the length of the gate electrode structure 151, the efficiency of these mechanisms may significantly decrease, thereby resulting in a less pronounced performance gain.
For these reasons, alternative transistor architectures have been proposed, such as “three-dimensional” architectures, in which a desired channel width and thus transistor width may be obtained at reduced overall lateral dimensions, while at the same time superior controllability of the current flow through the channel region may be achieved. To this end, so-called FinFETs have been proposed in which a thin sliver or fin of silicon may be formed in a thin layer of a semiconductor material, wherein at least on both sidewalls of the fin and possibly on a top surface thereof, a gate dielectric material and a gate electrode material may be provided, thereby realizing a double gate or tri-gate transistor whose channel region may be fully depleted. Typically, in sophisticated applications, the width of the silicon fins may be on the order of magnitude of 10-20 nm and the height thereof may be on the order of magnitude of 30-40 nm.
Thus, FinFET transistor architectures may provide advantages with respect to increasing the effective coupling of the gate electrode to the various channel regions without requiring a corresponding reduction in thickness of the gate dielectric material. Moreover, by providing this non-planar transistor architecture, the effective channel width may also be increased so that, for given overall lateral dimensions of a transistor, an enhanced current drive may be obtained.
FIG. 1b schematically illustrates a perspective view of the semiconductor device 100 which comprises a FinFET transistor 120, which is to represent any three-dimensional or “vertical” transistor architecture. As illustrated, the device comprises the substrate 101 and the “buried” insulating layer 102 on which are formed a plurality of semiconductor fins 110, which may thus represent the “residues” of a portion of the semiconductor layer 103 (FIG. 1a). Moreover, a gate electrode structure 130 may be formed adjacent to a central portion of the semiconductor fins 110 so as to define corresponding channel regions therein. It should be appreciated that the gate electrode structure 130 may comprise a gate dielectric material formed on sidewalls 110a, 110b of the semiconductor fins 110 and also typically on a top surface 110s of the fins 110. In this case, the sidewalls 110a, 110b and the top surface 110s may represent the actual control areas for controlling a current flow through the semiconductor fins 110 so that sometimes this transistor structure is referred to as a tri-gate configuration. Consequently, each of the fins 110 may comprise a source region 122 and a drain region 123 which may represent respective end portions of the fins 110 and which may thus have an appropriate dopant concentration in order to form corresponding PN junctions with the channel region, which is covered by the gate electrode structure 130. Consequently, the semiconductor fins 110 may enable a controlled current flow along a length direction 110l, wherein the current flow may be controlled by the gate electrode structure 130. For this purpose, a height 110h and a width 110w of the fins 110 may be appropriately selected in combination with the characteristics of the gate electrode structure 130 so as to obtain a reliable control of the current flow. As previously discussed, for given lateral dimensions of the transistor 120, a significantly increased overall drive current may be obtained, while patterning of the gate electrode structure 130 may be less critical, for instance with respect to a thickness of a gate dielectric material.
Typically, the semiconductor device 100 comprising the three-dimensional transistor 120 may be formed on the basis of appropriate patterning techniques in which the semiconductor fins 110 may be formed on the basis of sophisticated lithography and etch techniques in order to etch through the initial semiconductor layer 103 (FIG. 1a), while using the buried insulating layer 102 as an etch stop material, or forming recesses of a desired depth into the semiconductor material, if a bulk architecture is considered. Thereafter, the gate electrode structure is formed, for instance, by adding a desired gate dielectric material, such as a silicon oxide-based material, which may be accomplished by oxidation and/or deposition, followed by the deposition of an electrode material, such as polysilicon and the like. After providing the gate layer stack, appropriate lithography and etch techniques may be applied in order to form the gate electrode structure 130 having a desired “gate length,” indicated as 1301. Thus, a desired short gate length may be obtained wherein, nevertheless, superior controllability is achieved since the gate control voltage may be applied from both sidewalls 110a, 110b and the top surface 110s, contrary to the planar transistor 150 as illustrated in FIG. 1a. The drain and source regions 122, 123 may be formed on the basis of ion implantation processes and the like in accordance with any appropriate process strategy.
In order to further enhance performance of the transistor 120, it has been proposed to also apply strain-inducing mechanisms, similar as described with reference to the planar transistor 150 of FIG. 1a. In view of further device scaling, however, many of these strain-inducing mechanisms are considered as less efficient, such as stressed spacers and stressed overlayers. With respect to device generations using transistors having critical dimensions of 30 nm and less, in particular the incorporation of a strain-inducing semiconductor material, such as a silicon/germanium alloy, into the drain and source areas is considered most promising in view of achieving a gain in performance of three-dimensional transistor architectures. Other strain-inducing mechanisms that are considered as potential candidates with respect to three-dimensional transistors are providing metal gate electrode structures in which the metal material may be provided with a high internal stress level, while, in other cases, globally strained base semiconductor materials are considered as representing promising strain-inducing mechanisms. However, the latter candidates for a strain-inducing mechanism, i.e., globally strained semiconductor layers and metal gate electrode structures, are presently not fully understood with respect to their effect on actual transistor architectures. On the other hand, the strain-inducing mechanism based on silicon/germanium, as is well established for planar transistors, is believed to provide superior performance for P-channel transistors only, thereby only partially contributing to transistor performance in CMOS devices. Since, generally, strain-inducing mechanisms are considered as promising approaches for further enhancing overall performance of complex transistor architectures, possibly in combination with the introduction of sophisticated high-k metal gate electrode structures, the present disclosure relates to manufacturing techniques and semiconductor devices in which transistor performance may be enhanced on the basis of a strain-inducing mechanism in semiconductor devices including three-dimensional transistor architectures, possibly in combination with planar transistors, while avoiding or at least reducing the effects of one or more of the problems identified above.